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Clock Frequency | 60MHz |
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Organization | 547 CLBS, 2000 GATES |
Number of Logic Cells | 295 |
Surface Mount | YES |
Number of CLBs | 547 |
Terminal Position | QUAD |
Package / Case | 68-LCC (J-Lead) |
Technology | CMOS |
JESD-30 Code | S-PQCC-J68 |
Voltage - Supply | 4.5V~5.5V |
Number of Inputs | 57 |
Terminal Form | J BEND |
Number of Terminations | 68 |
Supply Voltage | 5V |
Number of Equivalent Gates | 2000 |
Width | 24.2316mm |
Qualification Status | Not Qualified |
RoHS Status | Non-RoHS Compliant |
Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
Operating Temperature | 0°C~70°C TA |
HTS Code | 8542.39.00.01 |
Number of LABs/CLBs | 295 |
Number of I/O | 57 |
Mounting Type | Surface Mount |
Power Supplies | 5V |
Pin Count | 68 |
Number of Outputs | 57 |
Series | ACT™ 1 |
Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY |
Length | 24.2316mm |
Subcategory | Field Programmable Gate Arrays |
Packaging | Tray |
Part Status | Obsolete |
Number of Gates | 1200 |
Published | 1997 |
Terminal Pitch | 1.27mm |
Reach Compliance Code | unknown |
Base Part Number | A1010 |
Combinatorial Delay of a CLB-Max | 3.4 ns |
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